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DATA SHEET
O K I A S I C P R O D U C T S
MG113P/114P/115P/73P/74P/75P 0.25m Sea of Gates and Customer Structured Arrays
November 1999
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Oki Semiconductor
MG113P/114P/115P/73P/74P/75P
0.25m Sea of Gates and Customer Structured Arrays DESCRIPTION
Oki's 0.25m Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25m drawn (0.18m L-effective) CMOS technology. The SOG MG113P/114P series uses the same SOG base-array architecture as the MG115P series, but offers four and three metal layers, respectively. The MG73P/74P CSA series uses three and four metal layers, respectively. The semiconductor process is adapted from Oki's production-proven 64Mbit DRAM manufacturing process. The 0.25m family provides significant performance, density, and power improvement over previous 0.30 and 0.35m technologies. An innovative 4-transistor cell structure, licensed from In-Chip Systems, Inc., provides 30 to 50% less power and 30 to 50% more usable gates than traditional cell designs. The Oki 0.25m family operates using 2.5-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal MG113P/114P/115P SOG series contains 4 array bases, offering up to 588 I/O pads and over 2.4M raw gates. The 3-, 4-, and 5-layer metal MG73P/74P/75P CSA series contains 21 array bases, offering up to 868 I/O pads and over 5.4M raw gates. These SOG and CSA array sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array (PBGA) packages. The MG113P/114P/115P series SOG architecture allows rapid prototyping turnaround times (TATs), additionally offering the most cost-effective solution for pad-limited circuits (particularly the 3-layer metal MG113P series). The 3-layer-metal MG73P, 4-layer-metal MG74P and 5-layer-metal MG75P CSA series contains 21 array bases, offering a wider span of gate and I/O counts than the SOG series. Oki uses the Artisan Components memory compiler which provides high performance, embedded synchronous single- and dual-port RAM macrocells for CSA designs. As such, the MG73P/74P/75P series is suited to memory-intensive ASICs and high-volume designs where fine tuning of package size produces significant cost or real-estate savings.
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FEATURES
* * * * * 0.25m drawn 3-, 4-, and 5-layer metal CMOS Optimized 2.5-V core Optimized 3-V I/O SOG and CSA architecture availability 77-ps typical gate propagation delay (for a 4xdrive inverter gate with a fanout of 2 and 0 mm of wire, operating at 2.5 V) Over 5.4M raw gates and 868 I/O pads using 60 staggered I/O User-configurable I/O with VSS, VDD, TTL, 3-state, and 1- to 24-mA options Slew-rate-controlled outputs for low-radiated noise H-clock tree cells which reduces the maximum skew for clock signals * Low 0.2W/MHz/gate power dissipation * User-configurable single- and dual-port memories * Specialized IP cores and macrocells including 32-bit ARM7TDMI CPU, phase-locked loop (PLL), and peripheral component interconnect (PCI) cells * Floorplanning for front-end simulation, backend layout controls, and link to synthesis * Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG) * Support for popular CAE systems including Cadence, IKOS, Mentor Graphics, Model Technology, Inc. (MTI), Synopsys, and Viewlogic
* * * *
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MG113P/114P/115P/73P/74P/75P FAMILY LISTING
60m Staggered PAD products No. of Pads 68 108 148 188 228 268 308 348 388 428 468 508 548 588 628 668 708 748 788 828 868 No. of Rows 84 144 204 264 324 384 444 504 564 624 684 744 804 864 924 984 1,044 1,104 1,164 1,224 1,284 No. of Columns 280 480 680 880 1,080 1,280 1,480 1,680 1,880 2,080 2,280 2,480 2,680 2,880 3,080 3,280 3,480 3,680 3,880 4,080 4,280 No. of Raw Gates 23,520 69,120 138,720 232,320 349,920 491,520 657,120 846,720 1,060,320 1,297,920 1,559,920 1,845,120 2,154,720 2,488,320 2,845,920 3,227,520 3,633,120 4,062,720 4,516,320 4,993,920 5,495,520 1,094,861 732,974 572,573 387,701 MG113P/73P Family 3LM Usable Gates MG114P/74P Family 4LM Usable Gates 22,344 65,664 131,784 218,381 311,429 412,877 519,125 635,040 763,430 882,586 982,498 1,107,072 1,249,738 1,393,459 1,536,797 1,678,310 1,816,560 1,950,106 2,077,507 2,197,325 2,308,118 MG115P/75P Family 5LM Usable Gates 22,344 65,664 131,784 220,704 332,424 466,944 611,122 745,114 901,272 1,025,357 1,154,045 1,310,035 1,465,210 1,642,291 1,821,389 2,001,062 2,179,872 2,356,378 2,529,139 2,696,717 2,857,670
SOG Base Array
EA Base Array MG7xPB02 MG7xPB04 MG7xPB06 MG7xPB08 MG7xPB10 MG7xPB12
MG11xP14 MG11xP18 MG11xP22
MG7xPB14 MG7xPB16 MG7xPB18 MG7xPB20 MG7xPB22 MG7xPB24 MG7xPB26
MG11xP28
MG7xPB28 MG7xPB30 MG7xPB32 MG7xPB34 MG7xPB36 MG7xPB38 MG7xPB40 MG7xPB42
ARRAY ARCHITECTURE
The primary components of a 0.25m MG113P/114P/115P circuit include: * * * * * * * * * I/O base cells 60m pad pitch Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility Innovative 4-transistor core cell architecture, licensed from In-Chip Systems, Inc
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO).
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I/O base cells
Separate power bus (VDDC, VSSC) for internal core logic (2nd metal/3rd metal)
Configurable I/O pads for VDD, VSS, or I/O
1, 2, 3, 4, or 5 layer metal interconnection in core area
Core base cell with 4 transistors
VDD, VSS pads (4) in each corner for wafer probing only
Separate power bus (VDDO, VSSO) over I/O cell for output buffers (2nd metal/3rd metal)
Figure 7. MG115P Array Architecture
MG73P/74P/75P CSA Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify macrocell functions required and minimum array size to hold macrocell functions. - Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design's megacells. - Oki Design Center engineers verify the master slice and review simulation. - Oki Design Center or customer engineers floorplan the array using Oki's supported floorplanner or Cadence DP3 or Gambit GFP and customer performance specifications. - Using Oki CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer's specifications.
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Figure 8 shows an array base after placement of the optimized memory macrocells.
High-density RAM
Mega macrocells
Figure 8. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 9 marks the area in which placement and routing is performed with cross hatching.
Figure 9. Random Logic Place and Route
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (VSS = 0 V, TJ = 25C) [1]
Parameter Power supply voltage Symbol VDD Core (2.5 V) VDD I/O (3.3 V) Input voltage (Input Buffer) Output voltage (Output Buffer) Input current (Input Buffer) Output current per I/O (Output Buffer) Storage temperature VI VO II IO TSTG Rated Value -0.3 to +3.6 -0.3 to +4.6 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -10 to +10 -24 to +24 -65 to +150 mA C V Unit
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (VSS = 0 V)
Parameter Power supply voltage Symbol VDD Core (2.5 V) VDD I/O (3.3 V) Junction temperature Tj Rated Value +2.25 to +2.75 +3.0 to +3.6 -40 to +85 Unit V C
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DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 3.0 to 3.6 V, VSS = 0 V, Tj = -40 to +85C)
Rated Value Parameter High-level input voltage Low-level input voltage TTL- level Schmitt Trigger input buffer Threshold voltage High-level output voltage (Output buffer) Symbol VIH VIL Vt+ VtVt VOH Vt+ - VtIOH = -100 A, VDD = VDD I/O IOH = -1, -2, -4, -6, -8, -12, -24 mA Low-level output voltage (Output buffer) VOL IOL = 100 A IOL = 1, 2, 4, 6, 8, 12, 24 mA High-level input current (Input buffer) IIH VIH = VDD VIH = VDD (50-k pull-down) Low-level input current (Normal input buffer) IIL VIL = VSS VIL = VSS (50-k pull-up) VIL = VSS (3-k pull-up) 3-state output leakage current (Normal input buffer) IOZH VOH = VDD VOH = VDD (50-k pull-down) IOZL VOL = VSS VOL = VSS (50-k pull-up) VOL = VSS (3-k pull-up) Stand-by current [2] IDDQ Output open, VIH = VDD, VIL = VSS Conditions TTL input (normal), VDD = VDD I/O TTL input (normal) TTL input Min. 2.0 -0.3 - 0.7 0.4 VDD -0.2 2.4 - - - 10 -10 -200 -3.3 -10 10 -10 -200 -3.3 Typ. - - 1.5 1.0 0.5 - - - - - 66 - -66 -1.1 - 66 - -66 -1.1 Design Dependent
[1]
Max. VDD +0.3 0.8 2.0 - - - - 0.2 0.4 10 200 10 -10 -0.3 10 200 10 -10 -0.3
Unit
V
A
mA
A
mA A
1. Typical condition is VDD I/O = 3.3 V, VDD Core = 2.5 V, and Tj = 25C on a typical process. 2. RAM/ROM should be in powerdown mode.
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DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 3.0 to 3.6 V, VSS = 0 V, Tj = -40 to +125C)
Rated Value Parameter High-level input voltage Low-level input voltage TTL- level Schmitt Trigger input buffer Threshold voltage High-level output voltage (Output buffer) Symbol VIH VIL Vt+ VtVt VOH Vt+ - VtIOH = -100 A, VDD=VDD I/O IOH = -1, -2, -4, -6, -8, -12, -24 mA Low-level output voltage (Output buffer) VOL IOL = 100 A IOL = 1, 2, 4, 6, 8, 12, 24 mA High-level input current (Input buffer) IIH VIH = VDD VIH = VDD (50-k pull-down) Low-level input current (Normal input buffer) IIL VIL = VSS VIL = VSS (50-k pull-up) VIL = VSS (3-k pull-up) 3-state output leakage current (Normal input buffer) IOZH VOH = VDD VOH = VDD (50-k pull-down) IOZL VOL = VSS VOL = VSS (50-k pull-up) VOL = VSS (3-k pull-up) Stand-by current [2] IDDQ Output open, VIH = VDD, VIL = VSS Conditions TTL input (normal), VDD=VDD I/O TTL input (normal) TTL input Min. 2.0 -0.3 - 0.7 0.4 VDD - 0.2 2.35 - - - 10 -50 -200 -3.3 -50 10 -50 -200 -3.3 Typ. - - 1.5 1.0 0.5 - - - - - 66 - -66 -1.1 - 66 - -66 -1.1 Design Dependent
[1]
Max. VDD + 0.3 0.8 2.0 - - - - 0.2 0.45 50 200 50 -10 -0.3 50 200 50 -10 -0.3
Unit
V
A
mA
A
mA A
1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25C for a typical process. 2. RAM/ROM should be in powerdown mode.
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DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 2.25 to 2.75 V, VSS = 0 V, Tj = -40 to +125C)
Rated Value Parameter High-level input voltage Low-level input voltage TTL- level Schmitt Trigger input buffer Threshold voltage High-level output voltage (Output buffer) Symbol VIH VIL Vt+ VtVt VOH Vt+ - VtIOH = -100 A, VDD=VDD I/O IOH = -0.5, -1, -2, -3, -4, -6, -12 mA Low-level output voltage (Output buffer) VOL IOL = 100 A IOL = -0.5, 1, 2, 3, 4, 6, 12 mA High-level input current (Input buffer) Low-level input current (Normal input buffer) IIH IIL VIH = VDD VIL = VSS VIL = VSS (3-k pull-up) 3-state output leakage current (Normal input buffer) IOZH IOZL VOH = VDD VOL = VSS VOL = VSS (3-k pull-up) Stand-by current [2] IDDQ Output open, VIH = VDD, VIL = VSS Conditions TTL input (normal), VDD=VDD I/O TTL input (normal) TTL input (normal) Min. 1.7 -0.3 0.6 VDD - 0.2 1.95 -50 -50 -50 -50 Typ. 0.4 -0.8 -0.8 Design Dependent
[1]
Max. VDD + 0.3 0.7 1.7 0.2 0.45 50 50 50 50 -
Unit
V
A mA A mA A
1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25C for a typical process. 2. RAM/ROM should be in powerdown mode.
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AC Characteristics (Core VDD = 2.5 V, VSS = 0 V, Tj = 25C)
Parameter Internal gate propagation delay Inverter Driving Type 1X 2X 4X 2-input NAND 1X 2X 4X 2-input NOR 1X 4X Inverter 1X 2X 4X 2-input NAND 1X 2X 4X 2-input NOR 1X 4X Toggle frequency F/O = 1, L = 0 mm F/O = 2, L = standard wire length VDD = 2.5 V F/O = 2, L = 0 mm VDD = 2.5 V Conditions
[1] [2]
Rated Value 0.080 0.072 0.061 0.118 0.102 0.094 0.134 0.127 0.204 0.159 0.108 0.274 0.183 0.136 0.329 0.219 1100
[3]
Unit
ns
MHz
1. Input transition time in 0.15 ns / 2.5 V. 2. Typical condition is VDD = 2.5 V and Tj = 25oC for a typical process. 3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.
AC Characteristics (I/O VDD = 3.3 V, VSS = 0 V, Tj = 25C)
Parameter Input buffer propagation delay Output buffer propagation delay Push-pull Normal output buffer 4 mA 8 mA 12mA Output buffer transition time
[1]
Conditions F/O = 2, L = standard wire length CL = 20 pF CL = 50 pF CL = 100 pF CL = 100 pF CL = 100 pF
Rated Value 0.311 1.783 2.011 2.562 3.325 (r) 3.043 (f)
Unit ns ns ns ns ns ns
Push-pull Normal output buffer
12 mA 12 mA
1. Output rising and falling times are both specified over a 10 to 90% range.
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MACRO LIBRARY
Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available.
Examples Basic Macrocells NANDs NORs EXORs Latches Flip-Flops Combinational Logic
Basic Macrocells with Scan Test
Flip-Flops
Clock Tree Driver Macrocells Macrocells 3-V Output Macrocells 3-State Outputs Push-Pull Outputs Open Drain Outputs Slew Rate Control Outputs PCI Outputs
MSI Macrocells
Counters Shift Registers
Mega/Special Macrocells [1] Macro Library 3-V Input Macrocells
ARM7TDMI PLL
Inputs Inputs with Pull-Downs Inputs with Pull-Ups
3-V Bi-Directional Macrocells
I/O PCI I/O
I/O with Pull-Downs I/O with Pull-Ups
Oscillator Macrocells
Gated Oscillators
Memory Macrocells
SOG RAMs: Single-Port RAMs Dual-Port RAMs
Optimized Diffused RAMs: Single-Port RAMs Dual-Port RAMs
Macrofunctions
MSI Macrofunctions
[1] Under development
4-Bit Register/Latches
Figure 10. Oki Macrocell and Macrofunction Library
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Macrocells for Driving Clock Trees Oki offers clock-tree drivers that minimize clock skew. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include: * * * * * * * True RC back annotation of the clock network Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Automatic branch length minimization Dynamic driver placement Up to four clock trunks
Clock
Figure 11. Clock Tree Structure
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OKI ADVANCED DESIGN CENTER CAD TOOLS
Oki's advanced design center CAD tools include support for the following: * * * * Floorplanning for front-end simulation and back-end layout control Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements
Vendor Cadence
Platform HP9000, 7xx IBM RS6000 Sun(R) [2]
Operating System [1] HP-UX AIX SunOS, Solaris
Vendor Software/Revision [1] ComposerTM VerilogTM NC-VerilogTM VeritimeTM VerifaultTM ConceptTM [3] LeapfrogTM NSIM Gemini/Voyager IDEATM QuickVHDL QuickSim IITM DFT Advisor Fastscan V-System
Description Design capture Simulation Simulation Timing analysis Fault grading Design capture VHDL simulation Simulation Design capture VHDL simulation Logic simulation Test synthesis ATPG VHDL simulation
IKOS Mentor GraphicsTM
HP9000, 7xx, Sun [2] HP9000, 7xx Sun [2]
HP-UX, SunOS, Solaris HP-UX SunOS, Solaris
Model Technology Inc. (MTI) Synopsys (Interface to Mentor Graphics, VIEWLogic) VIEWLogic
HP9000, 7xx Sun [2] PC IBM RS6000 HP9000, 7xx Sun [2] PC Sun [2]
HP-UX SunOS, Solaris Win/NTTM AIX HP-UX SunOS, Solaris WindowsTM, Win/NTTM [4] SunOS, Solaris
Design CompilerTM HDL/VHDL CompilerTM Test CompilerTM VSSTM PowerviewTM Fusion HDL
Compilation Design synthesis Test synthesis VHDL simulation Simulation VHDL/VerilogTM Simulation
1. 2. 3. 4.
Contact Oki Application Engineering for current software versions. Sun or Sun-compatible. Sun and HP platform only. In development.
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Design Process The following figure illustrates the overall IC design process, also indicating the three main interface points between external design houses and Oki ASIC Application Engineering.
Level 1 [5] VHDL/HDL Description Synthesis LSF[2] Floorplanning Gate-Level Simulation Test Vectors
CAE Front-End
Level 2 Netlist Conversion (EDIF 200) Scan Insertion (Optional) CDC [1] Floorplanning Pre-Layout Simulation (Cadence Verilog) Test Vector Conversion (Oki TPL [4]) TDC [3]
Level 2.5 [5] Layout Fault Simulation [6] Oki Interface Automatic Test Pattern Generation (Synopsys Test Compiler)
Verification (Cadence DRACULA)
Post-Layout Simulation (Cadence Verilog)
Level 3 [5] Manufacturing Prototype Test Program Conversion
[1] [2] [3] [4] [5] [6]
Oki's Circuit Data Check program (CDC) verifies logic design rules Oki's Link to Synthesis Floorplanning toolset (LSF) transfers post-floorplanning timing for resynthesis Oki's Test Data Check program (TDC) verifies test vector rules Oki's Test Pattern Language (TPL) Alternate Customer-Oki design interfaces available in addition to standard level 2 Standard design process includes fault simulation
Figure 12. Oki's Design Process
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Automatic Test Pattern Generation Oki's 0.25m ASIC technologies support ATPG using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction
ATPG methodology is described in detail in Oki's 0.25m Scan Path Application Note.
Combinational Logic A FD1AS D C SD SS Q B FD1AS D C SD SS Q Scan Data Out
Scan Data In
QN
QN
Scan Select
Figure 13. Full Scan Path Configuration Floorplanning Design Flow Oki offers two floorplanning tools for high-density ASIC design: Cadence DP3, and Gambit GFP. The two main purposes for Oki's floorplanning tools are to: * Ensure conformance of critical circuit performance specifications * Shorten overall design TAT In a traditional design approach with synthesis tools, timing violations after prelayout simulation are fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using predicted interconnection delay due to wire length. Synthesis tools may therefore create over-optimized results. To minimize these problems, Synopsys proposed a methodology called, "Links to Layout (LTL)". Based on this methodology, Oki developed an interface between Oki's Floorplanner and the Synopsys environment, called Link Synopsys to Floorplanner (LSF). As not every Synopsys user has access to the Synopsys Floorplan Management tool, Oki had developed the LSF system to support both users who can access Synopsys Floorplan Management and users who do not have access to Synopsys Floorplan Management.
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More information on OKI's floorplanning capabilities is available in Oki's Application Note, Using Oki's Floorplanner: Standalone Operation and Links to Synopsys.
Incremental Optimization with Physical Information Initial Synthesis HDL Entry No Constraints Met? Yes Invoke Import on Floorplanner Constraints Met? Gate Level Netlist (EDIF) Yes Initial Floorplan No Incremental Floorplan PDEF (Synopsis)
Constraints
Synthesis
Gate Level Netlist (EDIF)
DSPF/Oki RC/ PDEF (Synopsys) Wire Load Model (Synopsys) Net Capacitance (Synopsys Script (Synopsys)
Invoke Export on Floorplanner Invoke Delay
Delay (SDF)
Load Back-Annotation Files
Constraints Met? = In Synopsys DC/DA = In Floorplanner Yes To Simulation and P&R
No Timing Optimization
Figure 14. LSF System Design Flow
IEEE JTAG Boundary Scan Support Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: * * * * * * Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register
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Oki's boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki supports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technologies. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki's JTAG Boundary Scan Application Note. (Contact the Oki Application Engineering Department for interface options.)
PACKAGE OPTIONS
TQFP, LQFP and QFP Package Menu
LQFP Base Array Product Name MG7xPB02 MG7xPB04 MG7xPB06 MG7xPB08 MG7xPB10 MG7xPB12 MG11xP14 MG7xPB14 MG7xPB16 MG11xP18 MG7xPB18 MG7xPB20 MG11xP22 MG7xPB22 MG7xPB24 MG7xPB26 MG11xP28 MG7xPB28 MG7xPB30 MG7xPB32 MG7xPB34 MG7xPB36 MG7xPB38 MG7xPB40 MG7xPB42 Body Size (mm) Lead Pitch (mm) I/O Pads 68 108 148 188 228 268 308 348 388 428 468 508 548 588 628 668 708 748 788 828 868
q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q
[1]
QFP 208 208 240
TQFP 100
q q q q q q q q q q q q q
144
176
20 x 20 0.5
24 x 24 0.5
28 x 28 0.5
28 x 28 0.5
32 x 32 0.5
14 x 14 0.5
1. I/O Pads can be used for input, output, bi-directional, power, or ground. q = Available now
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BGA Package Menu
BGA Base Array Product Name MG7xPB02 MG7xPB04 MG7xPB06 MG7xPB08 MG7xPB10 MG7xPB12 MG11xP14 MG7xPB14 MG7xPB16 MG11xP18 MG7xPB18 MG7xPB20 MG11xP22 MG7xPB22 MG7xPB24 MG7xPB26 MG11xP28 MG7xPB28 MG7xPB30 MG7xPB32 MG7xPB34 MG7xPB36 MG7xPB38 MG7xPB40 MG7xPB42 Body Size (mm) Lead Pitch (mm) Ball Count Signal I/O Power Ball GND Ball 1. I/O Pads can be used for input, output, bi-directional, power, or ground. q = Available now I/O Pads 68 108 148 188 228 268 308 348 388 428 468 508 548 588 628 668 708 748 788 828 868 27x27 1.27 256 231 12 13 35x35 1.27 352 304 16 32 35x35 1.27 420 352 32 36
q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q
[1]
256
352
420
560
35x35 1.00 560 400 80 80
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Oki Semiconductor
The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 1999 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki.
Oki Semiconductor
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